1. Field of the Invention
The present invention relates to a fabrication process of a solid-state image pick-up device with a CCD register which can improve a tolerance voltage of an insulation layer formed between transfer electrodes.
2. Description of the Prior Art
FIG. 1 is a plan view illustrating a construction of the conventional CCD type two-dimensional solid-state image pick-up device. A plurality of photodiodes 101 for photoelectric conversion are arranged in a form of a matrix array on a substrate. Vertical CCD registers 102 for transferring a charge in vertical direction are provided between respective row of the photodiodes 101. A horizontal CCD register 103 for transferring a charge in the horizontal direction is connected to the vertical CCD registers 102. A charge detector 104 for detecting a charge and an amplifier 105 for amplifying the output of the charge detector 104 are connected to one end of the horizontal CCD register 103.
In the solid-state image pick-up device constructed as set forth above, an image pattern is projected on the solid-state image pick-up device, at first. Then, charge depending upon intensity of the incident light on each of photodiodes 101 arranged in the matrix array is accumulated in each individual photodiode 101. Next, as time elapsed, the accumulated charge is shifted in the direction shown by arrow 110 and thus transferred to the vertical CCD register 102.
Next, the charge is transferred to the vertical CCD register 102 in the direction shown by arrow 111, to reach the horizontal CCD register 103. Subsequently, the charge is transferred in the horizontal CCD register 103 in a direction shown by arrow 112. Then, the charge is converted into a voltage in the charge detector 104 and thereafter output via the amplifier 105.
FIG. 2 is an illustration showing a part of section taken along line II--II of FIG. 1. A structure of unit pixel of the conventional CCD type two-dimensional solid-state image pick-up device will be discussed with reference to FIG. 2. A P-type well layer 21 is formed on the surface of an N-type semiconductor substrate 11. An N-type impurity region 13 to be a photodiode is selectively formed on the surface of the well layer 21. A high density P-type impurity region 25 is formed on the surface of the N-type impurity region 13. One side of the P-type impurity region 25 is positioned inside of the N-type impurity region 13 and the other side reaches the side surface of the N-type impurity region 13.
A P-type impurity region 26 to be a channel of MOS transistor is formed in the shallower region, adjacent one side of the N-type impurity region 13. An N-type impurity layer 15 to form the CCD register is formed adjacent the P-type impurity region 26. Also, a P-type impurity layer 23 is formed in a region facing with the lower surface of the N-type impurity layer 15. A high density P-type impurity layer 24 for isolation device is formed adjacent the other side of the N-type impurity region 13. The N-type impurity layer 15 and the P-type impurity layer 23 forming CCD register are formed via the P-type impurity layer 24.
Also, a gate insulation layer 31 is formed over the entire surface. A charge transfer electrode group 41 of polycrystalline silicon is formed selectively except for the region aligned with the P-type impurity region 25 on the surface of the gate insulation layer 31. On the entire surface of these, an interlayer insulation layer 33 is formed. A light shielding layer 51 preventing light from penetrating into a CCD channel (N-type impurity layer 15) is formed in a region aligning with the charge transfer electrode group 41 on the surface of the interlayer insulation layer 33.
In the unit pixel constructed as set forth above, a pn junction photodiode is formed with the N-type impurity region 13 and the P-type well layer 21. Accordingly, an incident light 61 of the N-type impurity region 13 from the upper side of the device is subject photoelectric conversion. Electron generated by this is accumulated in the N-type impurity region 13. At this time, the high density P-type impurity region 25 serves for reducing current generated at Si/SiO.sub.2 interface.
On the other hand, a MOS transistor is formed with the N-type impurity region 13, the CCD channel (N-type impurity layer 15) and the P-type impurity region 26. Accordingly, when a voltage pulse in a range of 10 to 15 V is applied to the charge transfer electrode group 41, the charge accumulated in the photodiode (N-type impurity region 13) can be transferred to the CCD channel (N-type impurity layer 15).
Subsequently, applying a voltage pulse in a range of -5 to -10 V to the charge transfer electrode group 41, the electron is transferred in the CCD channel (N-type impurity layer 15) in the direction shown by arrow 111 in FIG. 1. At this time, since the P-channel impurity region 26 serving as a channel of the MOS transistor becomes in cut-off condition, the charge accumulated in the photodiode (N-type impurity region 13) will never be discharged to the CCD channel.
FIG. 3 is a section taken along line III--III of FIG. 1. Structure of the CCD register of the conventional CCD type two-dimensional solid-state image pick-up device will be described with reference to FIG. 3. In FIG. 3, the N-type semiconductor substrate 11 and the P-type impurity layer 23 shown in FIG. 2 has been neglected.
As shown in FIG. 3, the N-type impurity layer 15 is formed on the surface of the P-type well layer (semiconductor substrate) 21. The gate insulation layer 31 is formed on the surface of the N-type impurity layer 15.
First transfer electrodes 4 made of a polycrystalline silicon are formed with a given interval on the surface of the gate insulation layer 31, and the surface thereof is covered with a thermal oxide layer 6. Second transfer electrodes 5 made of polycrystalline silicon are formed via the thermal oxide layer 6 between respective of the first transfer electrodes 4. The charge transfer electrode group 41 is formed with these first transfer electrodes 4 and the second transfer electrodes 5. Also, the first transfer electrodes 4 and the second transfer electrodes 5 are connected to four voltage supply lines 7a, 7b, 7c and 7d, respectively in the sequential order of arrangement of the lines.
In the CCD register constructed as set forth above, the foregoing voltage pulse in the range of -5 to -10 V is applied to the first transfer electrodes 4 and the second transfer electrodes 5 forming the charge transfer electrode group 41. FIG. 4 is an illustration showing a voltage pulse waveform to be applied to the transfer electrodes from the voltage supply lines 7a to 7d. Four phase pulse voltages of .phi.a to .phi.d are applied from the four voltage supply lines 7a to 7d. As the pulse voltage, a pulse voltage having a reference voltage of 0 V and amplitude of -5 to -10 V may be employed, for example. Then, the electron is transferred in the N-type impurity layer 15 as the CCD channel in the direction shown by allow 111.
FIGS. 5A to 5D are sections showing fabrication process of the CCD register in order of sequence. As shown in FIG. 5A, the N-type impurity layer 15 is formed on the surface of the P-type well layer 21, employing known technology. Then, the gate insulation layer 31 is formed on the N-type impurity layer 15.
Next, as shown in FIG. 5B, a polycrystalline silicon layer (not shown) is deposited on the surface of the gate insulation layer 31 by way of CVD method or the like. By selectively removing the polycrystalline silicon layer, the first transfer electrodes 4 are formed. It should be noted that, upon deposition of the polycrystalline silicon, if impurity such as phosphorous or the like, is not doped in the polycrystalline silicon layer, a process step to diffuse impurity, such as phosphorous by way of thermal diffusion method after deposition of the polycrystalline silicon layer. Next, the thermal oxide layer 6 is formed by thermal oxidation of the surface of the first transfer electrode 4.
Subsequently, over these surfaces, a polycrystalline silicon layer 5a is deposited.
Then, as shown in FIG. 5D, a portion of the polycrystalline silicon layer 5a above the first transfer electrodes 4 is selectively removed. By this, the second transfer electrodes 5 are formed. The conventional CCD register is thus fabricated.
A In the conventional CCD register, the charge transfer electrode group 41 has a function to read out the charge from the photodiodes (N-type impurity region 13) to the vertical CCD channel (N-type impurity layer 15) and a function to transfer the charge in the CCD channel. Accordingly, the pulse voltage in a range up to 15 V is applied to the thermal oxide layer 6 isolating between the first transfer electrodes 4 and the second transfer electrodes 5.
However, the thermal oxide layer 6 formed by thermal oxidation of the surface of the first transfer electrode 4 made of the polycrystalline silicon, has low tolerance voltage, and, in general, can obtain electric field strength of merely about 1 to 2 (MV/cm). Accordingly, in order to obtain the tolerance voltage of 15 V, the thermal oxide layer 6 should be formed in the thickness greater than or equal to 0.2 .mu.m. Particularly, in case of the solid-state image pick-up device having large area, lack of tolerance voltage of the thermal oxide layer 6 inherently lower yield significantly.
When the thickness of the thermal oxide layer 6 is increased seeking for improvement of the tolerance voltage, a step to be formed between the portion where the first and second transfer electrodes 4 and 5 overlap to each other and the portion where the transfer electrodes are not formed (photodiode portion) becomes greater than or equal to 1 .mu.m. By this, coverage of the metal electrode layer (light shielding layer 51) to be formed on the surface of the charge transfer electrode group 41 is lowered at the step portion and the metal electrode layer becomes thin in the vicinity of the step portion. If the thin layer portion is formed in the metal electrode layer, and the light penetrates into the CCD register, the penetrated light is converted into the charge by photoelectric conversion in the CCD. Then, such charge is added to the signal charge to be a pseudo signal to cause lowering of S/N ratio.
When the metal electrode layer (light shielding layer 51) is used as wiring, breakage of the wiring can be caused at the step portion. By this, voltage cannot be applied to the transfer electrode.
In this fact, in the insulation layer between the polycrystalline silicon layers to be the transfer electrode, it has been strongly demanded to form insulation layer which is thin in the thickness and can improve tolerance voltage.
In general, as one of causes of low tolerance voltage of the thermal oxide layer (insulation layer) formed on the polycrystalline silicon layer, the surface of the polycrystalline silicon layer at the interface between the polycrystalline silicon layer and the thermal oxide layer after thermal oxidation is unevenness. Thus, for planarizing the surface of the polycrystalline silicon layer to improve the tolerance voltage of the thermal oxide layer, there has been proposed a method to perform oxidation of the surface of the polycrystalline silicon layer to be the transfer electrode at high temperature higher than or equal to 1000.degree. C. (R. M. Anderson et al., "Evidence for surface asperity mechanism of conductivity in oxide grown on polycrystalline silicon", Journal of Applied Physics, Vol. 48, No. 11, 1977, pp 4834-4836). This will be hereinafter referred to as "first prior art".
When the thermal oxide layer is formed by the first prior art, mechanical strain caused at the interface of the polycrystalline silicon layer and the thermal oxide layer can be reduced by oxidation process at high temperature to reduce unevenness at the interface.
Also, there has been proposed a method to planarizing the surface of the polycrystalline silicon layer. (K, Shinada et al., "Reduction in Polysilicon Oxide Leakage Current by Annealing prior to Oxidation", Journal of Electrochemical Society, SOLID-STATE SCIENCE AND TECHNOLOGY, Vol. 132, No. 9, 1985, pp 2185-2188). The proposed technology is to enlarge crystal grain size of the polycrystalline silicon layer by appropriately defining phosphorous concentration in the polycrystalline silicon or by performing annealing process to the polycrystalline silicon layer before oxidation of the surface of the polycrystalline silicon layer, for planarizing the surface of the polycrystalline silicon. This will be hereinafter referred to as "second prior art".
Also, there has been proposed a method for reducing unevenness of interface between the polycrystalline silicon and the thermal oxide layer for improving tolerance voltage by providing annealing process for the thermal oxide layer at high temperature after oxidation of the polycrystalline silicon layer. (D. K. Brown et al., "Ramp Breakdown Study of Double Polysilicon RAM's as a Function of Fabrication Parameters", Journal of Electrochemical Society, SOLID-STATE SCIENCE AND TECHNOLOGY, Vol. 130, No. 7, 1983, pp 1597-1603). This will be hereinafter referred to as "third prior art". However, even by the first to third prior arts set forth above, it has not been possible to sufficiently improve the tolerance voltage of the insulation layer. Furthermore, since the foregoing prior arts require heat treatment at high temperature higher than or equal to 1000 .degree. C, if such prior art is applied to the solid-state image pickup device, diffusion depth of the PN junction can be restricted. Accordingly, these technology is difficult to apply for the solid-state image pick-up device.